The April 13, 2026 cliff in Note 1 to ECCN 3A090.a is gone. BIS moved Approved IC Designer applications to 31 December 2026. The final rule published 9 April 2026. It took effect 7 April. If your internal plan still said April, it is wrong.

The news

Federal Register document 2026-06851, docket 260406-0093, RIN 0694-AJ98, revises the Export Administration Regulations. The summary says BIS is extending by about eight months the triggering date for authorized integrated circuit designer status and the submission date for applications to become an approved IC designer. The new date is 31 December 2026.

The rule amends Note 1 to ECCN 3A090.a in Supplement No. 1 to Part 774, replacing "April 13, 2026" with "December 31, 2026" wherever that date appeared in paragraphs (2) and (3). Applications must be received by 31 December 2026. After that date, applicants may be considered authorized IC designers for 180 days while review proceeds.

The framework traces to BIS's 16 January 2025 interim final rule on additional due-diligence measures for advanced computing integrated circuits (90 FR 5298). That rule added presumptions affecting front-end fabricators and OSAT companies exporting or transferring applicable advanced logic integrated circuits under ECCN 3A090.a unless the presumption is overcome. Note 1 lists pathways involving Approved IC designers (Supplement No. 6 to Part 740), approved OSAT companies, or authorized IC designers meeting criteria in the note.

BIS's newsroom text, posted with the rule, says the April 7, 2026 extension gives companies more time to submit Approved IC Designer applications and gives BIS more time to process them. The newsroom points to the Federal Register for the full language.

Who is bound

BIS issued the rule under the Export Administration Regulations. Integrated circuit designers seeking approved or authorized status are directly bound. Front-end fabricators and OSAT firms relying on Note 1 to 3A090.a to overcome license presumptions for applicable advanced logic ICs are affected when a partner's designer status lapses or stays pending.

Export compliance at fabless chip companies, semiconductor IP licensors, and systems houses that buy advanced accelerators are bound indirectly. Classification and end-user statements have to reflect current designer-list status. Freight already classified under a prior authorized-designer assumption should be re-checked against the extended window and the 180-day authorized period.

What's new

Entities that missed internal deadlines for ERC submissions gain roughly eight months. BIS cites processing capacity as the reason. That is not a reversal of the January 2025 due-diligence structure.

Approved IC designers already listed in Supplement No. 6, including major U.S. and allied fabless names published in the January 2025 rule, keep listed status. The extension mainly hits companies still moving from authorized to approved status under the note.

What it does not settle

Dates: rule effective 7 April 2026; Federal Register publication 9 April 2026; application deadline 31 December 2026; 180-day authorized period after a timely application, per the rule text. Hardware scope: ECCN 3A090.a applicable advanced logic integrated circuits under § 742.6(a)(6)(iii)(A). Region: authorized-designer criteria still use headquarters and ultimate-parent location rules from the January 2025 framework, including Country Group D:5 and Macau restrictions in the underlying IFR. Cost: BIS estimates incremental advisory-opinion and AES reporting burden in the rule; no new license fee line. Whether ERC throughput will clear all pending applications by year-end is UNKNOWN.

What to do now

Trade compliance should calendar 31 December 2026 for Approved IC Designer submissions and map which open export classifications depend on Note 1 pathways. Supply-chain should request updated designer-status attestations from fabless partners before booking long-lead advanced-logic shipments.

Which entities receive ERC approval before 31 December 2026 is UNKNOWN.